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2cad22a22a
** Add simulation context (VerilatedContext) to allow multiple fully independent
models to be in the same process. Please see the updated examples.
** Add context->time() and context->timeInc() API calls, to set simulation time.
These now are recommended in place of the legacy sc_time_stamp().
55 lines
1.2 KiB
Systemverilog
55 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This model counts from 0 to 10. It is instantiated twice in concurrent
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// threads to check for race conditions/signal interference.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020-2021 by Andreas Kuster.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module top
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(
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input clk,
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input rst,
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input [31:0] trace_number,
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input stop,
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output bit [31:0] counter,
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output bit done_o
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);
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initial begin
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string number;
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string filename;
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number.itoa(trace_number);
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filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".vcd"};
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$display("Writing dumpfile '%s'", filename);
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$dumpfile(filename);
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$dumpvars();
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end
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always@(posedge clk) begin
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if (rst)
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counter <= 0;
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else
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counter <= counter + 1;
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end
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always_comb begin
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done_o = '0;
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if (stop) begin
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if (counter >= 5 && stop) begin
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done_o = '1;
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$stop;
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end
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end
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else begin
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if (counter >= 10) begin
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done_o = '1;
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$finish;
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end
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end
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end
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endmodule
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