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16 lines
360 B
Systemverilog
16 lines
360 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Legal with ANSI Verilog 2001 style ports
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module t
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(
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output wire ok_ow,
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output reg ok_or);
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wire ok_o_w;
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reg ok_o_r;
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endmodule
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