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138 lines
3.8 KiB
Systemverilog
138 lines
3.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2030 by Stephen Henry.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int fdin_bin, fdout_txt, fdout_bin;
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`define STRINGIFY(x) `"x`"
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`define checkh(gotv,expv) \
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do if ((gotv) !== (expv)) begin\
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$write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));\
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end while(0)
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//
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//
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task automatic test1; begin
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for (int i = 0; i < 256; i++) begin
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byte actual, expected;
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expected = i[7:0];
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$fscanf(fdin_bin, "%u", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%u", actual);
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end
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for (int i = 0; i < 256; i++) begin
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shortint actual, expected;
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for (int j = 0; j < 2; j++)
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expected[(8 * j)+:8] = i[7:0] + j[7:0];
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$fscanf(fdin_bin, "%u", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%u", actual);
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end
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for (int i = 0; i < 256; i++) begin
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int actual, expected;
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for (int j = 0; j < 4; j++)
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expected[(8 * j)+:8] = i[7:0] + j[7:0];
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$fscanf(fdin_bin, "%u", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%u", actual);
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end
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for (int i = 0; i < 256; i++) begin
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longint actual, expected;
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for (int j = 0; j < 8; j++)
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expected[(8 * j)+:8] = i[7:0] + j[7:0];
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$fscanf(fdin_bin, "%u", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%u", actual);
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end
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end endtask
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//
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//
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task automatic test2; begin
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for (int i = 0; i < 256; i++) begin
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byte actual, expected;
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expected = i[7:0];
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$fscanf(fdin_bin, "%z", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%z", actual);
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end
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for (int i = 0; i < 256; i++) begin
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shortint actual, expected;
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for (int j = 0; j < 2; j++)
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expected[(8 * j)+:8] = i[7:0] + j[7:0];
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$fscanf(fdin_bin, "%z", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%z", actual);
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end
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for (int i = 0; i < 256; i++) begin
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int actual, expected;
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for (int j = 0; j < 4; j++)
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expected[(8 * j)+:8] = i[7:0] + j[7:0];
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$fscanf(fdin_bin, "%z", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%z", actual);
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end
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for (int i = 0; i < 256; i++) begin
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longint actual, expected;
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for (int j = 0; j < 8; j++)
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expected[(8 * j)+:8] = i[7:0] + j[7:0];
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$fscanf(fdin_bin, "%z", actual);
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`checkh(actual, expected);
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$fdisplay(fdout_txt, "%h", actual);
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$fwrite(fdout_bin, "%z", actual);
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end
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end endtask
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initial begin : main_PROC
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string filename;
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filename = "t/t_sys_file_basic_uz.dat";
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fdin_bin = $fopen(filename, "rb");
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`ifdef IVERILOG
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filename = $sformatf("%s/t_sys_file_basic_uz_test.log","obj_iv/t_sys_file_basic_uz");
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`else
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filename = $sformatf("%s/t_sys_file_basic_uz_test.log",`STRINGIFY(`TEST_OBJ_DIR));
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`endif
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fdout_txt = $fopen(filename, "w");
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`ifdef IVERILOG
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filename = $sformatf("%s/t_sys_file_basic_uz_test.bin","obj_iv/t_sys_file_basic_uz");
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`else
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filename = $sformatf("%s/t_sys_file_basic_uz_test.bin",`STRINGIFY(`TEST_OBJ_DIR));
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`endif
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$display(filename);
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fdout_bin = $fopen(filename, "wb");
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test1;
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test2;
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$fclose(fdin_bin);
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$fclose(fdout_txt);
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$write("*-* All Finished *-*\n");
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$finish(0); // Test arguments to finish
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end // block: main_PROC
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`undef STRINGIFY
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endmodule // t
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