mirror of
https://github.com/verilator/verilator.git
synced 2025-01-10 16:47:48 +00:00
422c076fec
This support code merely adds the capability to skip over the encrypted parts. Many models have unencrypted module interfaces with ports, and only encrypt the critical parts.
1027 lines
21 KiB
Plaintext
1027 lines
21 KiB
Plaintext
`line 1 "t/t_preproc.v" 1
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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2000-2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`line 6 "t/t_preproc.v" 0
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//===========================================================================
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// Includes
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`line 8 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc2.vh" 1
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// DESCRIPTION: Verilog::Preproc: Example source code
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`line 2 "t/t_preproc_inc2.vh" 0
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2000-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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At file "t/t_preproc_inc2.vh" line 5
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`line 7 "t/t_preproc_inc2.vh" 0
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`line 1 "t/t_preproc_inc3.vh" 1
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`line 2 "inc3_a_filename_from_line_directive" 0
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// DESCRIPTION: Verilog::Preproc: Example source code
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2000-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`line 7 "inc3_a_filename_from_line_directive" 0
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// FOO
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At file "inc3_a_filename_from_line_directive" line 11
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`line 13 "inc3_a_filename_from_line_directive" 0
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// guard
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`line 16 "inc3_a_filename_from_line_directive" 0
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`line 20 "inc3_a_filename_from_line_directive" 2
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`line 7 "t/t_preproc_inc2.vh" 0
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`line 9 "t/t_preproc_inc2.vh" 2
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`line 8 "t/t_preproc.v" 0
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`line 10 "t/t_preproc.v" 0
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//===========================================================================
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// Comments
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`line 13 "t/t_preproc.v" 0
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/* verilator pass_thru comment */
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`line 15 "t/t_preproc.v" 0
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// verilator pass_thru_comment2
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`line 17 "t/t_preproc.v" 0
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//===========================================================================
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// Defines
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`line 20 "t/t_preproc.v" 0
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// DEF_A0 set by command line
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wire [3:0] q = {
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1'b1 ,
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1'b0 ,
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1'b1 ,
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1'b1
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};
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`line 30 "t/t_preproc.v" 0
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text.
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`line 32 "t/t_preproc.v" 0
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foo /*this */ bar /* this too */
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foobar2 // but not
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`line 37 "t/t_preproc.v" 0
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`line 41 "t/t_preproc.v" 0
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`line 46 "t/t_preproc.v" 0
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/*******COMMENT*****/
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first part
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`line 47 "t/t_preproc.v" 0
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second part
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`line 47 "t/t_preproc.v" 0
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third part
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{
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`line 48 "t/t_preproc.v" 0
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a,
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`line 48 "t/t_preproc.v" 0
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b,
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`line 48 "t/t_preproc.v" 0
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c}
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Line_Preproc_Check 49
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`line 51 "t/t_preproc.v" 0
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//===========================================================================
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`line 53 "t/t_preproc.v" 0
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`line 55 "t/t_preproc.v" 0
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deep deep
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`line 59 "t/t_preproc.v" 0
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"Inside: `nosubst"
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"`nosubst"
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`line 64 "t/t_preproc.v" 0
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x y LLZZ x y
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p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s
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`line 70 "t/t_preproc.v" 0
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firstline comma","line LLZZ firstline comma","line
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`line 72 "t/t_preproc.v" 0
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x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not
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`line 75 "t/t_preproc.v" 0
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(a,b)(a,b)
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`line 78 "t/t_preproc.v" 0
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$display("left side: \"right side\"")
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`line 81 "t/t_preproc.v" 0
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bar_suffix more
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`line 84 "t/t_preproc.v" 0
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`line 86 "t/t_preproc.v" 0
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$c("Zap(\"",bug1,"\");");;
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`line 87 "t/t_preproc.v" 0
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$c("Zap(\"","bug2","\");");;
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`line 89 "t/t_preproc.v" 0
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/* Define inside comment: `DEEPER and `WITHTICK */
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// More commentary: `zap(bug1); `zap("bug2");
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`line 92 "t/t_preproc.v" 0
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//======================================================================
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// display passthru
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`line 95 "t/t_preproc.v" 0
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initial begin
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//$display(`msg( \`, \`)); // Illegal
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$display("pre thrupre thrumid thrupost post: \"right side\"");
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$display("left side: \"right side\"");
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$display("left side: \"right side\"");
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$display("left_side: \"right_side\"");
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$display("na: \"right_side\"");
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$display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\"");
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$display("na: \"nana\"");
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$display("left_side right_side // Doesn't expand: \"left_side right_side // Doesn't expand\""); // Results vary between simulators
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$display(": \"\""); // Empty
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$display("left side: \"right side\"");
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$display("left side: \"right side\"");
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$display("standalone");
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`line 116 "t/t_preproc.v" 0
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// Unspecified when the stringification has multiple lines
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$display("twoline: \"first second\"");
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//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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`line 126 "t/t_preproc.v" 0
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//======================================================================
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// rt.cpan.org bug34429
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`line 129 "t/t_preproc.v" 0
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`line 134 "t/t_preproc.v" 0
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module add1 ( input wire d1, output wire o1);
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`line 135 "t/t_preproc.v" 0
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wire tmp_d1 = d1;
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`line 135 "t/t_preproc.v" 0
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wire tmp_o1 = tmp_d1 + 1;
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`line 135 "t/t_preproc.v" 0
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assign o1 = tmp_o1 ; // expansion is OK
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endmodule
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module add2 ( input wire d2, output wire o2);
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`line 138 "t/t_preproc.v" 0
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wire tmp_d2 = d2;
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`line 138 "t/t_preproc.v" 0
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wire tmp_o2 = tmp_d2 + 1;
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`line 138 "t/t_preproc.v" 0
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assign o2 = tmp_o2 ; // expansion is bad
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endmodule
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`line 141 "t/t_preproc.v" 0
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`line 147 "t/t_preproc.v" 0
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// parameterized macro with arguments that are macros
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`line 152 "t/t_preproc.v" 0
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`line 152 "t/t_preproc.v" 0
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generate for (i=0; i<(3); i=i+1) begin
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`line 152 "t/t_preproc.v" 0
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psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1";
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`line 152 "t/t_preproc.v" 0
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psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1";
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`line 152 "t/t_preproc.v" 0
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end endgenerate // ignorecmt
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`line 154 "t/t_preproc.v" 0
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//======================================================================
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// Quotes are legal in protected blocks. Grr.
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module prot();
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`protected
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I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
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#nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
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`line 160 "t/t_preproc.v" 0
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`endprotected
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endmodule
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//"
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`line 164 "t/t_preproc.v" 0
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//======================================================================
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// Check IEEE1800-2017 `pragma protect encrypted modules
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module t_lint_pragma_protected;
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`line 168 "t/t_preproc.v" 0
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`pragma protect begin_protected
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`pragma protect version=1
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`pragma protect encrypt_agent="XXXXX"
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`pragma protect encrypt_agent_info="YYYYY"
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`pragma protect data_method="AES128-CBC"
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`pragma protect key_keyowner="BIG3#1"
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`pragma protect key_keyname="AAAAAA"
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`pragma protect key_method="RSA"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`pragma protect key_block
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ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg
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KSAyMDA3IE==
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`line 181 "t/t_preproc.v" 0
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`pragma protect key_keyowner="BIG3#2"
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`pragma protect key_keyname="BBBBBB"
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`pragma protect key_method="RSA"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv
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cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs
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bG93ZWQuCgoKICBUaGl=
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`line 190 "t/t_preproc.v" 0
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`pragma protect key_keyowner="BIG3#3"
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`pragma protect key_keyname="CCCCCCCC"
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`pragma protect key_method="RSA"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g
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MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg
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YWRkaXRpb25hbCBwZXJ=
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`line 199 "t/t_preproc.v" 0
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295)
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`pragma protect data_block
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aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy
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c2lvbiAzIG9mIHRoZSBHTlUgTGVzc2VyCkdlbmVyYWwgUHVibGljIExpY2Vuc2UsIGFuZCB0aGUg
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IkdOVSBHUEwiIHJlZmVycyB0byB2ZXJzaW9uIDMgb2YgdGhlIEdOVQpHZW5lcmFsIFB1YmxpYyBM
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aWNlbnNlLgoKICAiVGhlIExpYnJhcnkiIHJlZmVycyB0byBhIGNvdmVyZWQgd29yayBnb3Zlcm5l
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ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l
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ZCBXb3JrIGFzIG==
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`line 209 "t/t_preproc.v" 0
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`pragma protect end_protected
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`line 211 "t/t_preproc.v" 0
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endmodule
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`line 213 "t/t_preproc.v" 0
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//======================================================================
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// macro call with define that has comma
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`line 223 "t/t_preproc.v" 0
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begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
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begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
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begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
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`line 227 "t/t_preproc.v" 0
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//======================================================================
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// include of parameterized file
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`line 230 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc4.vh" 1
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// DESCRIPTION: Verilog::Preproc: Example source code
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`line 2 "t/t_preproc_inc4.vh" 0
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2000-2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`line 6 "t/t_preproc_inc4.vh" 0
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`line 8 "t/t_preproc_inc4.vh" 2
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`line 230 "t/t_preproc.v" 0
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`line 231 "t/t_preproc.v" 0
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`line 234 "t/t_preproc.v" 0
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`line 236 "t/t_preproc.v" 0
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`line 240 "t/t_preproc.v" 0
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//======================================================================
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// macro call with , in {}
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`line 243 "t/t_preproc.v" 0
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$blah("ab,cd","e,f");
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$blah(this.logfile,vec);
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$blah(this.logfile,vec[1,2,3]);
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$blah(this.logfile,{blah.name(), " is not foo"});
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`line 249 "t/t_preproc.v" 0
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//======================================================================
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// pragma/default net type
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`line 252 "t/t_preproc.v" 0
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`pragma foo = 1
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`default_nettype none
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`default_nettype uwire
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`line 256 "t/t_preproc.v" 0
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//======================================================================
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// Ifdef
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`line 259 "t/t_preproc.v" 0
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`line 263 "t/t_preproc.v" 0
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Line_Preproc_Check 263
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`line 265 "t/t_preproc.v" 0
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//======================================================================
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// bug84
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`line 268 "t/t_preproc.v" 0
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// Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT?
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(p,q)
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`line 275 "t/t_preproc.v" 0
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(//Here x,y //Too)
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Line_Preproc_Check 276
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`line 278 "t/t_preproc.v" 0
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//======================================================================
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// defines split arguments
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`line 281 "t/t_preproc.v" 0
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beginend // 2001 spec doesn't require two tokens, so "beginend" ok
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beginend // 2001 spec doesn't require two tokens, so "beginend" ok
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"beginend" // No space "beginend"
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`line 289 "t/t_preproc.v" 0
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//======================================================================
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// bug106
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`\esc`def
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`line 295 "t/t_preproc.v" 0
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Not a \`define
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`line 297 "t/t_preproc.v" 0
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//======================================================================
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// misparsed comma in submacro
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x,y)--bee submacro has comma paren
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`line 305 "t/t_preproc.v" 0
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//======================================================================
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// bug191
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$display("10 %d %d", $bits(foo), 10);
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`line 310 "t/t_preproc.v" 0
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//======================================================================
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// 1800-2009
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`line 315 "t/t_preproc.v" 0
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`line 318 "t/t_preproc.v" 0
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//======================================================================
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// bug202
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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`line 332 "t/t_preproc.v" 0
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assign a3 = ~b3 ;
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`line 332 "t/t_preproc.v" 0
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`line 334 "t/t_preproc.v" 0
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/* multi \
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line1*/ \
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`line 336 "t/t_preproc.v" 0
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/*multi \
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line2*/
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`line 343 "t/t_preproc.v" 0
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`line 343 "t/t_preproc.v" 0
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`line 343 "t/t_preproc.v" 0
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/* multi
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line 3*/
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`line 343 "t/t_preproc.v" 0
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def i
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`line 345 "t/t_preproc.v" 0
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//======================================================================
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`line 347 "t/t_preproc.v" 0
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`line 351 "t/t_preproc.v" 0
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`line 357 "t/t_preproc.v" 0
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1 // verilator NOT IN DEFINE (nodef)
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2 /* verilator PART OF DEFINE */ (hasdef)
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3
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`line 359 "t/t_preproc.v" 0
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/* verilator NOT PART
|
|
OF DEFINE */ (nodef)
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`line 360 "t/t_preproc.v" 0
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4
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`line 360 "t/t_preproc.v" 0
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/* verilator PART
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|
OF DEFINE */ (nodef)
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`line 361 "t/t_preproc.v" 0
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5 also in
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`line 361 "t/t_preproc.v" 0
|
|
also3 // CMT NOT (nodef)
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HAS a NEW
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`line 364 "t/t_preproc.v" 0
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LINE
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`line 366 "t/t_preproc.v" 0
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//======================================================================
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`line 368 "t/t_preproc.v" 0
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`line 381 "t/t_preproc.v" 0
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`line 384 "t/t_preproc.v" 0
|
|
EXP: clxx_scen
|
|
clxx_scen
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EXP: clxx_scen
|
|
"clxx_scen"
|
|
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|
EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0);
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`line 390 "t/t_preproc.v" 0
|
|
do
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`line 390 "t/t_preproc.v" 0
|
|
/* synopsys translate_off */
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`line 390 "t/t_preproc.v" 0
|
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`line 390 "t/t_preproc.v" 0
|
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`line 390 "t/t_preproc.v" 0
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`line 390 "t/t_preproc.v" 0
|
|
if (start("t/t_preproc.v", 390)) begin
|
|
`line 390 "t/t_preproc.v" 0
|
|
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|
`line 390 "t/t_preproc.v" 0
|
|
message({"Blah-", "clx_scen", " end"});
|
|
`line 390 "t/t_preproc.v" 0
|
|
end
|
|
`line 390 "t/t_preproc.v" 0
|
|
/* synopsys translate_on */
|
|
`line 390 "t/t_preproc.v" 0
|
|
while(0);
|
|
|
|
`line 392 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
|
|
`line 394 "t/t_preproc.v" 0
|
|
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|
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|
|
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`line 398 "t/t_preproc.v" 0
|
|
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|
`line 398 "t/t_preproc.v" 0
|
|
|
|
|
|
`line 399 "t/t_preproc.v" 0
|
|
|
|
//`ifndef def_fooed_2 `error "No def_fooed_2" `endif
|
|
EXP: This is fooed
|
|
This is fooed
|
|
EXP: This is fooed_2
|
|
This is fooed_2
|
|
|
|
`line 406 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
|
|
np
|
|
np
|
|
//======================================================================
|
|
// It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution?
|
|
|
|
|
|
|
|
|
|
|
|
`line 417 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
`line 420 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
// Metaprogramming
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 428 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
`line 432 "t/t_preproc.v" 0
|
|
hello3hello3hello3
|
|
hello4hello4hello4hello4
|
|
//======================================================================
|
|
// Include from stringification
|
|
|
|
|
|
|
|
`line 438 "t/t_preproc.v" 0
|
|
`line 1 "t/t_preproc_inc4.vh" 1
|
|
// DESCRIPTION: Verilog::Preproc: Example source code
|
|
`line 2 "t/t_preproc_inc4.vh" 0
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2000-2011 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
`line 6 "t/t_preproc_inc4.vh" 0
|
|
|
|
|
|
`line 8 "t/t_preproc_inc4.vh" 2
|
|
`line 438 "t/t_preproc.v" 0
|
|
|
|
`line 439 "t/t_preproc.v" 0
|
|
|
|
//======================================================================
|
|
// Defines doing defines
|
|
// Note the newline on the end - required to form the end of a define
|
|
|
|
|
|
|
|
|
|
|
|
`line 447 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
Line_Preproc_Check 451
|
|
//======================================================================
|
|
// Quoted multiline - track line numbers, and ensure \\n gets propagated
|
|
|
|
|
|
|
|
Line_Preproc_Check 457
|
|
"FOO \
|
|
BAR " "arg_line1 \
|
|
arg_line2" "FOO \
|
|
BAR "
|
|
`line 460 "t/t_preproc.v" 0
|
|
Line_Preproc_Check 460
|
|
//======================================================================
|
|
// bug283
|
|
|
|
`line 464 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
// EXP: abc
|
|
|
|
abc
|
|
|
|
|
|
|
|
|
|
`line 474 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
EXP: sonet_frame
|
|
sonet_frame
|
|
|
|
`line 480 "t/t_preproc.v" 0
|
|
|
|
|
|
EXP: sonet_frame
|
|
sonet_frame
|
|
// This result varies between simulators
|
|
|
|
|
|
EXP: sonet_frame
|
|
sonet_frame
|
|
|
|
`line 490 "t/t_preproc.v" 0
|
|
// The existance of non-existance of a base define can make a difference
|
|
|
|
|
|
EXP: module zzz ; endmodule
|
|
module zzz ; endmodule
|
|
module zzz ; endmodule
|
|
|
|
`line 497 "t/t_preproc.v" 0
|
|
|
|
EXP: module a_b ; endmodule
|
|
module a_b ; endmodule
|
|
module a_b ; endmodule
|
|
|
|
`line 502 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
// bug311
|
|
integer/*NEED_SPACE*/ foo;
|
|
//======================================================================
|
|
// bug441
|
|
module t;
|
|
//-----
|
|
// case provided
|
|
// note this does NOT escape as suggested in the mail
|
|
|
|
|
|
|
|
initial begin : \`LEX_CAT(a[0],_assignment)
|
|
`line 514 "t/t_preproc.v" 0
|
|
$write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end
|
|
//-----
|
|
// SHOULD(simulator-dependant): Backslash doesn't prevent arguments from
|
|
// substituting and the \ staying in the expansion
|
|
// Note space after name is important so when substitute it has ending whitespace
|
|
|
|
|
|
initial begin : \a[0]_assignment_a[1]
|
|
`line 521 "t/t_preproc.v" 0
|
|
$write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end
|
|
|
|
//-----
|
|
|
|
|
|
// RULE: Ignoring backslash does NOT allow an additional expansion level
|
|
// (Because ESC gets expanded then the \ has it's normal escape meaning)
|
|
initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end
|
|
|
|
//-----
|
|
|
|
|
|
|
|
// Similar to above; \ does not allow expansion after substitution
|
|
initial begin : \`CAT(ff,bb)
|
|
`line 535 "t/t_preproc.v" 0
|
|
$write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end
|
|
|
|
//-----
|
|
|
|
|
|
// MUST: Unknown macro with backslash escape stays as escaped symbol name
|
|
initial begin : \`zzz
|
|
`line 541 "t/t_preproc.v" 0
|
|
$write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end
|
|
|
|
//-----
|
|
|
|
|
|
|
|
// SHOULD(simulator-dependant): Known macro with backslash escape expands
|
|
initial begin : \`FOO
|
|
`line 548 "t/t_preproc.v" 0
|
|
$write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end
|
|
// SHOULD(simulator-dependant): Prefix breaks the above
|
|
initial begin : \xx`FOO
|
|
`line 550 "t/t_preproc.v" 0
|
|
$write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end
|
|
|
|
//-----
|
|
// MUST: Unknown macro not under call with backslash escape doesn't expand
|
|
|
|
initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end
|
|
//-----
|
|
// MUST: Unknown macro not under call doesn't expand
|
|
|
|
initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end
|
|
|
|
//-----
|
|
// bug441 derivative
|
|
// SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above)
|
|
|
|
initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz");
|
|
|
|
//-----
|
|
// RULE: Because there are quotes after substituting STR, the `A does NOT expand
|
|
|
|
|
|
initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz");
|
|
|
|
//----
|
|
// bug845
|
|
|
|
initial $write("Slashed=`%s'\n", "1//2.3");
|
|
//----
|
|
// bug915
|
|
|
|
|
|
initial
|
|
`line 581 "t/t_preproc.v" 0
|
|
$display("%s%s","a1","b2c3\n");
|
|
endmodule
|
|
|
|
`line 584 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
//bug1225
|
|
|
|
`line 587 "t/t_preproc.v" 0
|
|
|
|
|
|
$display("RAM0");
|
|
$display("CPU");
|
|
|
|
`line 592 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
|
|
`line 597 "t/t_preproc.v" 0
|
|
|
|
XXE_FAMILY = XXE_
|
|
|
|
|
|
$display("XXE_ is defined");
|
|
|
|
|
|
`line 604 "t/t_preproc.v" 0
|
|
|
|
XYE_FAMILY = XYE_
|
|
|
|
|
|
$display("XYE_ is defined");
|
|
|
|
|
|
`line 611 "t/t_preproc.v" 0
|
|
|
|
XXS_FAMILY = XXS_some
|
|
|
|
|
|
$display("XXS_some is defined");
|
|
|
|
|
|
`line 618 "t/t_preproc.v" 0
|
|
|
|
XYS_FAMILY = XYS_foo
|
|
|
|
|
|
$display("XYS_foo is defined");
|
|
|
|
|
|
`line 625 "t/t_preproc.v" 0
|
|
//====
|
|
|
|
`line 627 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 635 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 642 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 649 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 656 "t/t_preproc.v" 0
|
|
|
|
|
|
`line 658 "t/t_preproc.v" 0
|
|
// NEVER
|
|
|
|
`line 660 "t/t_preproc.v" 0
|
|
//bug1227
|
|
|
|
(.mySig (myInterface.pa5),
|
|
|
|
`line 664 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
// Stringify bug
|
|
|
|
`line 667 "t/t_preproc.v" 0
|
|
|
|
`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
|
|
|
|
`line 670 "t/t_preproc.v" 0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
`line 678 "t/t_preproc.v" 0
|
|
module pcc2_cfg;
|
|
generate
|
|
|
|
`line 680 "t/t_preproc.v" 0
|
|
covergroup a @(posedge b);
|
|
`line 680 "t/t_preproc.v" 0
|
|
c: coverpoint d iff ((c) === 1'b1); endgroup
|
|
`line 680 "t/t_preproc.v" 0
|
|
a u_a;
|
|
`line 680 "t/t_preproc.v" 0
|
|
initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
|
|
endgenerate
|
|
endmodule
|
|
|
|
`line 684 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
// Verilog-Perl bug1668
|
|
|
|
"`NOT_DEFINED_STR"
|
|
|
|
`line 689 "t/t_preproc.v" 0
|
|
//======================================================================
|
|
// IEEE mandated predefines
|
|
// undefineall should have no effect on these
|
|
predef 0 0
|
|
predef 1 1
|
|
predef 2 2
|
|
predef 3 3
|
|
predef 10 10
|
|
predef 11 11
|
|
predef 20 20
|
|
predef 21 21
|
|
predef 22 22
|
|
predef 23 23
|
|
predef -2 -2
|
|
predef -1 -1
|
|
predef 0 0
|
|
predef 1 1
|
|
predef 2 2
|
|
//======================================================================
|
|
// After `undefineall above, for testing --dump-defines
|
|
|
|
|
|
`line 711 "t/t_preproc.v" 2
|