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26 lines
580 B
Systemverilog
26 lines
580 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2015 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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typedef struct packed {
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logic [3:0] msk;
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logic [3:0] dat;
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} STR_t;
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endpackage;
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package csr_pkg;
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typedef pkg::STR_t reg_t;
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localparam reg_t REG_RST = 8'h34;
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endpackage
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module t (/*AUTOARG*/);
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initial begin
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if (csr_pkg::REG_RST.msk != 4'h3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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