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31 lines
547 B
Systemverilog
31 lines
547 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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bl, cl, bc, cc,
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// Inputs
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a
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);
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input logic a;
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output logic bl;
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output logic cl;
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always_latch begin
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bl <= a; // No warning
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cl = a;
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end
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output logic bc;
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output logic cc;
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always_comb begin
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bc <= a; // Warning
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cc = a;
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end
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endmodule
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