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30 lines
914 B
Systemverilog
30 lines
914 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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function int f( int j = 1, int s = 0 );
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return (j<<16) | s;
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endfunction
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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initial begin
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`checkh( f(.j(2), .s(1)) , 32'h2_0001 );
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`checkh( f(.s(1)) , 32'h1_0001 );
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`checkh( f(, 1) , 32'h1_0001 );
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`checkh( f(.j(2)) , 32'h2_0000 );
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`checkh( f(.s(1), .j(2)) , 32'h2_0001 );
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`checkh( f(.s(), .j()) , 32'h1_0000 );
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`checkh( f(2) , 32'h2_0000 );
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`checkh( f() , 32'h1_0000 );
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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