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32 lines
656 B
Systemverilog
32 lines
656 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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cnt0, cnt1,
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// Inputs
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clk, clk1
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);
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input clk;
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input clk1;
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output int cnt0;
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output int cnt1;
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always @ (posedge clk) cnt0 <= cnt0 + 1;
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always @ (posedge clk1) cnt1 <= cnt1 + 1;
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final if (cnt0 == 0) $stop;
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final if (cnt1 != 0) $stop;
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always_comb begin
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if (cnt0==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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