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40 lines
787 B
Systemverilog
40 lines
787 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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int b;
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endclass
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class BaseExtended extends Base;
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int e;
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endclass
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module t;
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Base v_cls_a;
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BaseExtended v_cls_ab;
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BaseExtended v_cls_ab1;
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initial begin
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v_cls_a = Base'(null);
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if (v_cls_a != null) $stop;
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v_cls_ab = new;
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v_cls_ab.b = 10;
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v_cls_ab.e = 20;
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v_cls_ab1 = BaseExtended'(v_cls_ab);
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if (v_cls_ab1.b != 10) $stop;
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if (v_cls_ab1.e != 20) $stop;
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v_cls_a = Base'(v_cls_ab);
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if (v_cls_a.b != 10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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