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41 lines
1.0 KiB
Systemverilog
41 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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initial begin
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int tofind;
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int aliases[$];
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int found[$];
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int id;
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int i;
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aliases = '{ 1, 4, 6, 8};
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tofind = 6;
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found = aliases.find(i) with (i == tofind);
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// And as function
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aliases.find(i) with (i == tofind);
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// No parenthesis
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found = aliases.find with (item == i);
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aliases.find with (item == i);
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// Unique (array method)
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id = 4;
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found = aliases.unique with (id);
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found = aliases.unique() with (id);
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found = aliases.unique(i) with (id);
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i = aliases.or(v) with (v);
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i = aliases.and(v) with (v);
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i = aliases.xor(v) with (v);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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