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92 lines
2.4 KiB
Verilog
92 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [4*8:1] vstr;
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const string s = "a"; // Check static assignment
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string s2;
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string s3;
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reg eq;
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// Operators == != < <= > >= {a,b} {a{b}} a[b]
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// a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr
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// a.atoi, a.atohex, a.atooct, a.atobin, a.atoreal,
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// a.itoa, a.hextoa, a.octoa, a.bintoa, a.realtoa
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initial begin
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$sformat(vstr, "s=%s", s);
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`checks(vstr, "s=a");
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`checks(s, "a");
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`checks({s,s,s}, "aaa");
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`checks({4{s}}, "aaaa");
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// Constification
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`checkh(s == "a", 1'b1);
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`checkh(s == "b", 1'b0);
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`checkh(s != "a", 1'b0);
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`checkh(s != "b", 1'b1);
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`checkh(s > " ", 1'b1);
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`checkh(s > "a", 1'b0);
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`checkh(s >= "a", 1'b1);
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`checkh(s >= "b", 1'b0);
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`checkh(s < "a", 1'b0);
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`checkh(s < "b", 1'b1);
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`checkh(s <= " ", 1'b0);
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`checkh(s <= "a", 1'b1);
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end
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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s2 = "c0";
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end
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else if (cyc==1) begin
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$sformat(vstr, "s2%s", s2);
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`checks(vstr, "s2c0");
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end
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else if (cyc==2) begin
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s3 = s2;
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$sformat(vstr, "s2%s", s3);
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`checks(vstr, "s2c0");
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end
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else if (cyc==3) begin
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s2 = "a";
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s3 = "b";
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end
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else if (cyc==4) begin
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`checks({s2,s3}, "ab");
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`checks({3{s3}}, "bbb");
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`checkh(s == "a", 1'b1);
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`checkh(s == "b", 1'b0);
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`checkh(s != "a", 1'b0);
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`checkh(s != "b", 1'b1);
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`checkh(s > " ", 1'b1);
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`checkh(s > "a", 1'b0);
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`checkh(s >= "a", 1'b1);
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`checkh(s >= "b", 1'b0);
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`checkh(s < "a", 1'b0);
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`checkh(s < "b", 1'b1);
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`checkh(s <= " ", 1'b0);
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`checkh(s <= "a", 1'b1);
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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