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82 lines
1.9 KiB
Verilog
82 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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/*verilator no_inline_module*/ // So we'll get hiearachy we can test
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input clk;
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sub sub (/*AUTOINST*/
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// Inputs
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.clk (clk));
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endmodule
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module sub (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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/*verilator no_inline_module*/ // So we'll get hiearachy we can test
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integer cyc=0;
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reg [127:0] save128;
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reg [47:0] save48;
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reg [1:0] save2;
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reg [255:0] cycdone; // Make sure each cycle executes exactly once
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reg [31:0] vec[2:1][2:1];
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real r;
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string s,s2;
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string si;
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d\n",$time, cyc);
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`endif
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si = "siimmed";
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cyc <= cyc + 1;
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if (cycdone[cyc[7:0]]) $stop;
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cycdone[cyc[7:0]] <= '1;
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if (cyc==0) begin
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// Setup
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save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e;
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save48 <= 48'h4afe43fb79d7;
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save2 <= 2'b10;
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vec[1][1] <= 32'h0101;
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vec[1][2] <= 32'h0102;
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vec[2][1] <= 32'h0201;
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vec[2][2] <= 32'h0202;
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r <= 1.234;
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s <= "hello";
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end
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if (cyc==1) begin
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if ($test$plusargs("save_restore")!=0) begin
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// Don't allow the restored model to run from time 0, it must run from a restore
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$write("%%Error: didn't really restore\n");
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$stop;
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end
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end
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else if (cyc==99) begin
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if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop;
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if (save48 !== 48'h4afe43fb79d7) $stop;
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if (save2 !== 2'b10) $stop;
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if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop;
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if (vec[1][1] !== 32'h0101) $stop;
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if (vec[1][2] !== 32'h0102) $stop;
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if (vec[2][1] !== 32'h0201) $stop;
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if (vec[2][2] !== 32'h0202) $stop;
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if (r != 1.234) $stop;
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$display("%s",s);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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