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53 lines
1.5 KiB
Verilog
53 lines
1.5 KiB
Verilog
// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013.
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module t
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(
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input logic clk,
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input logic daten,
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input logic [8:0] datval,
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output logic signed [3:0][3:0][35:0] datao
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);
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logic signed [3:0][3:0][3:0][8:0] datat;
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genvar i;
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generate
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for (i=0; i<4; i++)begin
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testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i]));
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end
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endgenerate
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genvar j;
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generate
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for (i=0; i<4; i++) begin
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for (j=0; j<4; j++) begin
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always_comb datat[i][j][0] = daten ? 9'h0 : datval;
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always_comb datat[i][j][1] = daten ? 9'h1 : datval;
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always_comb datat[i][j][2] = daten ? 9'h2 : datval;
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always_comb datat[i][j][3] = daten ? 9'h3 : datval;
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end
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end
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endgenerate
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endmodule
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module testio
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(
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input clk,
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input logic signed [3:0] [3:0] [8:0] arr3d_in,
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output logic signed [3:0] [35:0] arr2d_out
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);
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logic signed [3:0] [35:0] ar2d_out_pre;
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always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
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always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
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always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
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always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
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always_ff @(posedge clk) begin
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if (clk)
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arr2d_out <= ar2d_out_pre;
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end
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endmodule
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