verilator/test_regress/t/t_lint_width_bad.out

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%Warning-WIDTH: t/t_lint_width_bad.v:16: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_lint_width_bad.v:38: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:20: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
%Error: Exiting due to