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85 lines
1.9 KiB
Verilog
85 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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/* Acceptable answer 1
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created tag with scope = top.t.tag
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created tag with scope = top.t.b.gen[0].tag
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created tag with scope = top.t.b.gen[1].tag
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mod a has scope = top.t
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mod a has tag = top.t.tag
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mod b has scope = top.t.b
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mod b has tag = top.t.tag
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mod c has scope = top.t.b.gen[0].c
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mod c has tag = top.t.b.gen[0].tag
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mod c has scope = top.t.b.gen[1].c
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mod c has tag = top.t.b.gen[1].tag
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*/
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/* Acceptable answer 2
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created tag with scope = top.t.tag
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created tag with scope = top.t.b.gen[0].tag
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created tag with scope = top.t.b.gen[1].tag
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mod a has scope = top.t
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mod a has tag = top.t.tag
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mod b has scope = top.t.b
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mod b has tag = top.t.tag
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mod c has scope = top.t.b.gen[0].c
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mod c has tag = top.t.tag
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mod c has scope = top.t.b.gen[1].c
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mod c has tag = top.t.tag
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*/
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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tag tag ();
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b b ();
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always @ (t.cyc) begin
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if (t.cyc == 2) $display("mod a has scope = %m");
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if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module b ();
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genvar g;
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generate
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for (g=0; g<2; g++) begin : gen
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tag tag ();
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c c ();
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end
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endgenerate
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always @ (t.cyc) begin
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if (t.cyc == 3) $display("mod b has scope = %m");
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if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
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end
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endmodule
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module c ();
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always @ (t.cyc) begin
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if (t.cyc == 4) $display("mod c has scope = %m");
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if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
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end
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endmodule
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module tag ();
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bit [100*8-1:0] scope;
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initial begin
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$sformat(scope,"%m");
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$display("created tag with scope = %0s",scope);
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end
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endmodule
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