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120 lines
2.1 KiB
Verilog
120 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003-2007 by Wilson Snyder.
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`define STRINGIFY(x) `"x`"
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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wire out;
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reg in;
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Genit g (.clk(clk), .value(in), .result(out));
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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in <= 1'b1;
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end
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else if (cyc==1) begin
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in <= 1'b0;
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end
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else if (cyc==2) begin
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if (out != 1'b1) $stop;
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end
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else if (cyc==3) begin
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if (out != 1'b0) $stop;
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end
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else if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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//`define WAVES
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`ifdef WAVES
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initial begin
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$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
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$dumpvars(12, t);
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end
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`endif
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endmodule
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module Generate (clk, value, result);
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input clk;
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input value;
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output result;
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reg Internal;
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assign result = Internal ^ clk;
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always @(posedge clk)
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Internal <= #1 value;
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endmodule
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module Checker (clk, value);
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input clk, value;
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always @(posedge clk) begin
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$write ("[%0t] value=%h\n", $time, value);
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end
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endmodule
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module Test (clk, value, result);
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input clk;
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input value;
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output result;
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Generate gen (clk, value, result);
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Checker chk (clk, gen.Internal);
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endmodule
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module Genit (clk, value, result);
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input clk;
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input value;
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output result;
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`ifndef ATSIM // else unsupported
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`ifndef NC // else unsupported
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`define WITH_FOR_GENVAR
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`endif
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`endif
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`define WITH_GENERATE
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`ifdef WITH_GENERATE
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`ifndef WITH_FOR_GENVAR
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genvar i;
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`endif
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generate
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for (
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`ifdef WITH_FOR_GENVAR
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genvar
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`endif
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i = 0; i < 1; i = i + 1)
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begin : foo
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Test tt (clk, value, result);
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end
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endgenerate
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`else
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Test tt (clk, value, result);
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`endif
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wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
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always @ (posedge clk) begin
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$write("[%0t] Result2 = %x\n", $time, Result2);
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end
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endmodule
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