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42 lines
685 B
Verilog
42 lines
685 B
Verilog
// DESCRIPTION: Verilator: Simple test of unoptflat
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//
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// Trigger the DETECTARRAY error.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Jeremy Bennett.
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localparam ID_MSB = 1;
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef struct packed {
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logic [ID_MSB:0] id;
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} context_t;
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context_t tsb;
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assign tsb.id = {tsb.id[0], clk};
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initial begin
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tsb.id = 0;
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end
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always @(posedge clk or negedge clk) begin
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`ifdef TEST_VERBOSE
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$write("tsb.id = %x\n", tsb.id);
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`endif
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if (tsb.id[1] != 0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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