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a8e06874bd
Broke in 7a04a5b
49 lines
1.3 KiB
Systemverilog
49 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define check_rand(cl, field, constr, cond) \
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begin \
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longint prev_result; \
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int ok = 0; \
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if (!bit'(cl.randomize() with { constr; })) $stop; \
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prev_result = longint'(field); \
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if (!(cond)) $stop; \
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repeat(9) begin \
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longint result; \
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if (!bit'(cl.randomize() with { constr; })) $stop; \
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result = longint'(field); \
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if (!(cond)) $stop; \
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if (result != prev_result) ok = 1; \
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prev_result = result; \
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end \
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if (ok != 1) $stop; \
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end
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class Cls #(int LIMIT = 3);
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rand int x;
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int y = -100;
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constraint x_limit { x <= LIMIT; };
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endclass
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module t;
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initial begin
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Cls#() cd = new;
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Cls#(5) c5 = new;
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`check_rand(cd, cd.x, x > 0, cd.x > 0 && cd.x <= 3);
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`check_rand(cd, cd.x, x > y, cd.x > -100 && cd.x <= 3);
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if (cd.randomize() with {x > 3;} == 1) $stop;
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`check_rand(c5, c5.x, x > 0, c5.x > 0 && c5.x <= 5);
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`check_rand(c5, c5.x, x > y, c5.x > -100 && c5.x <= 5);
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if (c5.randomize() with {x >= 5;} == 0) $stop;
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if (c5.x != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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