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745605efe3
DFG could remove forceable signals by replacing them with their in-design driver. This is a bit of a pain to prevent, and ideally the forcing transform should happen before DFG, but implementing it there is a pain due to having to rewrite ports based on direction. This is an attempted fix in DFG. More cases might remain.
84 lines
2.0 KiB
Systemverilog
84 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t (
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input wire clk,
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input wire rst,
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output reg [31:0] cyc
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);
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always @(posedge clk) begin
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if (rst) begin
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cyc <= 0;
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end else begin
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cyc <= cyc +1;
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end
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end
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`ifdef CMT
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wire net_1 /* verilator forceable */;
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wire [7:0] net_8 /* verilator forceable */;
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`else
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wire net_1;
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wire [7:0] net_8;
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`endif
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assign net_1 = ~cyc[0];
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assign net_8 = ~cyc[1 +: 8];
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wire obs_1 = net_1;
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wire [7:0] obs_8 = net_8;
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always @ (posedge clk) begin
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$display("%d: %x %x", cyc, obs_8, obs_1);
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if (!rst) begin
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case (cyc)
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3: begin
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`checkh (obs_1, 0);
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`checkh (obs_8, ~cyc[1 +: 8]);
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end
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4: begin
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`checkh (obs_1, 0);
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`checkh (obs_8, 8'h5f);
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end
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5: begin
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'h5f);
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end
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6, 7: begin
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'hf5);
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end
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8: begin
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`checkh (obs_1, ~cyc[0]);
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`checkh (obs_8, 8'hf5);
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end
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10, 11: begin
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`checkh (obs_1, 1);
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`checkh (obs_8, 8'h5a);
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end
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12, 13: begin
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`checkh (obs_1, 0);
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`checkh (obs_8, 8'ha5);
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end
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default: begin
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`checkh ({obs_8, obs_1}, ~cyc[0 +: 9]);
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end
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endcase
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end
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if (cyc == 30) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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