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15 lines
365 B
Systemverilog
15 lines
365 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls1;
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randc int rc;
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constraint c_bad { rc dist {3 := 0, 10 := 5}; } // Bad, no dist on randc
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endclass
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module t (/*AUTOARG*/);
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endmodule
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