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verilator/test_regress/t/t_clocking_bad1.out
2024-03-02 10:15:19 -05:00

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%Error: t/t_clocking_bad1.v:16:12: Only one default clocking block allowed per module (IEEE 1800-2023 14.12)
: ... note: In instance 't'
16 | default clocking @(posedge clk);
| ^~~~~~~~
%Error: Exiting due to