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54 lines
1.0 KiB
Verilog
54 lines
1.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc = 0;
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`ifdef iverilog
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reg [7:0] arr [3:0];
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wire [7:0] arr_w [3:0];
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`else
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reg [3:0] [7:0] arr;
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wire [3:0] [7:0] arr_w;
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`endif
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reg [7:0] sum;
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reg [7:0] sum_w;
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integer i0;
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initial begin
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for (i0=0; i0<5; i0=i0+1) begin
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arr[i0] = 1 << i0[1:0];
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end
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end
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assign arr_w = arr;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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sum <= 0;
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sum_w <= 0;
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end
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else if (cyc >= 10 && cyc < 14) begin
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sum <= sum + {4'b0,arr[cyc-10]};
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sum_w <= sum_w + {4'b0,arr_w[cyc-10]};
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum);
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if (sum != 8'h0f) $stop;
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if (sum != sum_w) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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