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26 lines
586 B
Systemverilog
26 lines
586 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module test;
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typedef enum { FOO_0 } foo_e;
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typedef enum { BAR_0 } bar_e;
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class baz #(parameter type E = foo_e);
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static function void print();
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E enum_item;
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if (enum_item.first().name() != "BAR_0")
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$stop;
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endfunction
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endclass
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initial begin
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baz#(bar_e)::print();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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