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f8c0169e82
Using the 'forceable' directive in a configuration file, or the /* verilator forceable */ metacomment on a variable declaration will generate additional public signals that allow the specified signals to be forced/released from the C++ code.
92 lines
2.2 KiB
Systemverilog
92 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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module t (
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input wire clk,
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input wire rst,
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output reg [31:0] cyc
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);
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always @(posedge clk) begin
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if (rst) begin
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cyc <= 0;
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end else begin
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cyc <= cyc +1;
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end
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end
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`ifdef CMT
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reg var_1 /* verilator forceable */;
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reg [7:0] var_8 /* verilator forceable */;
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`else
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reg var_1;
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reg [7:0] var_8;
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`endif
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always @(posedge clk) begin
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if (rst) begin
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var_1 <= 0;
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var_8 <= 0;
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end else begin
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var_1 <= cyc[0];
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var_8 <= cyc[1 +: 8];
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end
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end
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always @ (posedge clk) begin
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$display("%d: %x %x", cyc, var_8, var_1);
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if (!rst) begin
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case (cyc)
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0: begin // Reset values
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`checkh (var_1, 0);
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`checkh (var_8, 0);
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end
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13: begin
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`checkh (var_1, 1);
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`checkh ({1'b0, var_8}, (cyc[0 +: 9] - 1) >> 1);
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end
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14: begin
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`checkh (var_1, 1);
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`checkh (var_8, 8'hf5);
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end
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15: begin
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`checkh (var_1, 0);
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`checkh (var_8, 8'hf5);
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end
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16, 17: begin
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`checkh (var_1, 0);
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`checkh (var_8, 8'h5f);
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end
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18: begin
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`checkh (var_1, ~cyc[0]);
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`checkh (var_8, 8'h5f);
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end
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20, 21: begin
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`checkh (var_1, 1);
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`checkh (var_8, 8'h5a);
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end
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22, 23: begin
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`checkh (var_1, 0);
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`checkh (var_8, 8'ha5);
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end
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default: begin
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`checkh ({var_8, var_1}, cyc[0 +: 9] - 1);
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end
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endcase
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end
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if (cyc == 30) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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