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25 lines
542 B
Systemverilog
25 lines
542 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off UNOPTFLAT
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module t(
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input wire [3:0] i,
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output wire [2:0][3:0] o
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);
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wire [2:0][3:0] v;
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// This circular logic used to trip up DFG decomposition
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assign v[0] = i;
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assign v[1][0] = v[0][1] | v[0][0];
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assign o[1][2] = v[0][2];
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assign o[2][1:0] = {v[1][0] , o[1][0]};
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endmodule
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