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20 lines
376 B
Systemverilog
20 lines
376 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic unu3 = 0;
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logic isusd = 0;
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cover property (@(posedge clk) isusd == 0);
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endmodule
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