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21 lines
468 B
Systemverilog
21 lines
468 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic in, out;
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clocking cb @(posedge clk);
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default input #1 output #1step;
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default input #2 output #2;
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output #1step out;
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output out;
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endclocking
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endmodule
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