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599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
46 lines
1.1 KiB
Systemverilog
46 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] cyc; initial cyc = 0;
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reg genclk;
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// verilator lint_off MULTIDRIVEN
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reg [7:0] set_both;
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// verilator lint_on MULTIDRIVEN
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wire genthiscyc = ( (cyc % 2) == 1 );
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always @ (posedge clk) begin
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cyc <= cyc + 8'h1;
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genclk <= genthiscyc;
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set_both <= cyc;
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$write ("SB set_both %x <= cyc %x\n", set_both, cyc);
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if (genthiscyc) begin
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if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
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end
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else begin
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if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop;
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end
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @ (posedge genclk) begin
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set_both <= ~ set_both;
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$write ("SB set_both %x <= cyc %x\n", set_both, ~cyc);
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if (cyc>1 && set_both != (cyc - 8'h1)) $stop;
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end
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endmodule
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