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53 lines
1.3 KiB
Systemverilog
53 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Code your testbench here
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// or browse Examples
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class Base #(parameter PBASE = 12);
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bit [PBASE-1:0] member;
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function bit [PBASE-1:0] get_member;
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return member;
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endfunction
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function int get_p;
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return PBASE;
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endfunction
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endclass
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class Cls #(parameter P = 13) extends Base #(P);
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endclass
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typedef Cls#(8) Cls8_t;
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// See also t_class_param_mod.v
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module t (/*AUTOARG*/);
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Cls #(.P(4)) c4;
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Cls8_t c8;
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initial begin
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c4 = new;
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c8 = new;
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if (c4.PBASE != 4) $stop;
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if (c8.PBASE != 8) $stop;
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if (c4.get_p() != 4) $stop;
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if (c8.get_p() != 8) $stop;
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// verilator lint_off WIDTH
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c4.member = 32'haaaaaaaa;
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c8.member = 32'haaaaaaaa;
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// verilator lint_on WIDTH
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if (c4.member != 4'ha) $stop;
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if (c4.get_member() != 4'ha) $stop;
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if (c8.member != 8'haa) $stop;
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if (c8.get_member() != 8'haa) $stop;
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$display("c4 = %s", $sformatf("%p", c4));
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if ($sformatf("%p", c4) != "'{member:'ha}") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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