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This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
4 lines
147 B
Plaintext
4 lines
147 B
Plaintext
-V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] x)
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%Error: t/t_unopt_converge.v:7: Settle region did not converge.
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Aborting...
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