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28 lines
506 B
Systemverilog
28 lines
506 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 100ns/1ns
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module t;
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int ia;
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int ib;
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initial begin
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ia = 0;
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#1 ib = ++ia;
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#1
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if (ia !== ib) $stop;
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#1 ib = ia++;
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#1
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if (ia == ib) $stop;
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#10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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