verilator/test_regress/t/t_select_bad_msb.out

%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Little bit endian vector: left < right of bit range: [0:22]
                                             : ... In instance t
   12 |    reg [0:22] backwd;
      |        ^
                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Error: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1]
                                  : ... In instance t
   16 |       sel2 = mi[1:4];
      |                ^
%Error: Exiting due to