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87 lines
2.1 KiB
Systemverilog
87 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Methods defined by IEEE:
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// function int unsigned $urandom [ (int seed ) ] ;
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// function int unsigned $urandom_range( int unsigned maxval,
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// int unsigned minval = 0 );
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module t(/*AUTOARG*/);
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`ifndef VERILATOR
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`define PROC
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`endif
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`ifdef PROC
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process p;
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`endif
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int unsigned v1;
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int unsigned v2;
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int unsigned v3;
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string s;
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initial begin
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`ifdef PROC
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if (p != null) $stop;
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p = process::self();
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`endif
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v1 = $urandom;
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v2 = $urandom;
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v3 = $urandom();
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if (v1 == v2 && v1 == v3) $stop; // Possible, but 2^-64
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// Range
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v2 = $urandom_range(v1, v1);
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if (v1 != v2) $stop;
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v2 = $urandom_range(0, 32'hffffffff);
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if (v2 == v1) $stop;
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for (int test = 0; test < 20; ++test) begin
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v1 = 2;
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v1 = $urandom_range(0, v1);
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if (v1 != 0 && v1 != 1 && v1 != 2) $stop;
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v1 = $urandom_range(2, 0);
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if (v1 != 0 && v1 != 1 && v1 !=2) $stop;
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v1 = $urandom_range(3);
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if (v1 != 0 && v1 != 1 && v1 != 2 && v1 != 3) $stop;
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end
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// Seed stability
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// Note UVM doesn't use $urandom seeding
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v1 = $urandom(1);
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v2 = $urandom(1);
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if (v1 != v2) $stop;
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v2 = $urandom(1);
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if (v1 != v2) $stop;
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`ifdef PROC
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// Seed stability via process.srandom
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p.srandom(1);
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v1 = $urandom();
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p.srandom(1);
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v2 = $urandom();
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if (v1 != v2) $stop;
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p.srandom(1);
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v2 = $urandom();
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if (v1 != v2) $stop;
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// Seed stability via process.get_randstate
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s = p.get_randstate();
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v1 = $urandom();
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p.set_randstate(s);
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v2 = $urandom();
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if (v1 != v2) $stop;
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p.set_randstate(s);
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v2 = $urandom();
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if (v1 != v2) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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