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a2e1b32a1c
Before this change, some forked processes were being inlined in `V3Timing` because they contained no `CAwait`s. This only works under the assumption that no `CAwait`s will be added there later, which is not true, as a function called by a forked process could be turned into a coroutine later. The call would be wrapped in a new `CAwait`, but the process itself would have already been inlined at this point. This commit moves the inlining to `transformForks` in `V3SchedTiming`, which is called at a point when all `CAwait`s are already in place. Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
59 lines
1.3 KiB
Systemverilog
59 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clk = 0;
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assign #5 clk = ~clk;
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int a = 0;
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always @(posedge clk) begin
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a <= a + 1;
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`ifdef TEST_VERBOSE
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$display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v);
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`endif
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end
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int b = 0, c = 0, d = 0, e = 0, f = 0;
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always @a begin
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b = a << 1;
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fork
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#10 d = b + c;
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e = c + d;
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#5 f = d + e;
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join_none
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c = a + b;
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end
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logic[5:0] v;
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always @a begin
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v[0] = a[0];
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fork
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begin
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v[1] = a[1];
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#5 v[2] = a[2];
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end
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#10 v[3] = a[3];
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join_none
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v[4] = a[4];
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end
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initial #100 begin
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`ifdef TEST_VERBOSE
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$display("a=%0d, b=%0d, c=%0d, d=%0d, e=%0d, f=%0d, v=%b", a, b, c, d, e, f, v);
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`endif
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if (a != 10) $stop;
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if (b != 20) $stop;
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if (c != 30) $stop;
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if (d != 45) $stop;
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if (e != 75) $stop;
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if (f != 107) $stop;
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if (v != 'b001010) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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