verilator/test_regress/t/t_sv_cpu_code/timescale.sv
2020-03-21 11:24:24 -04:00

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Systemverilog

// DESCRIPTION: Verilator: Large test for SystemVerilog
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.
// SPDX-License-Identifier: CC0-1.0
// Contributed by M W Lund, Atmel Corporation.
// **** Set simulation time scale ****
`timescale 1ns/1ps