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96 lines
2.7 KiB
Systemverilog
96 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Large test for SystemVerilog
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012.
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// SPDX-License-Identifier: CC0-1.0
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// Contributed by M W Lund, Atmel Corporation.
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module pads
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#( parameter
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NUMPADS = $size( pinout )
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)
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(
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// ***************************************************************************
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// Module Interface
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// ***************************************************************************
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// **** Interfaces ****
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pads_if.mp_pads padsif,
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// **** Pinout ****
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`ifdef VERILATOR // see t_tri_array
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inout wire [NUMPADS:1] pad,
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`else
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inout wire pad [1:NUMPADS],
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`endif
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// **** Inputs ****
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input logic clk,
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input logic rst
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);
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// ***************************************************************************
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// Code Section
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// ***************************************************************************
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`ifdef VERILATOR // see t_tri_array
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tri [NUMPADS:1] _anahack;
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`endif
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genvar i;
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for ( i = 1; i <= NUMPADS; i++ )
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begin
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`ifdef VCS
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localparam t_padtype p_type = t_padtype'(pinout_wa[i][pinout_wa_padtype]);
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localparam t_pinid p_id = t_pinid'(pinout_wa[i][pinout_wa_id]);
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`else
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localparam t_padtype p_type = pinout[i].padtype;
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localparam t_pinid p_id = pinout[i].id;
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`endif
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case ( p_type )
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PADTYPE_GPIO:
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pad_gpio #( .ID( i ) )
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i_pad_gpio(
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.pad (pad [i]),
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// Outputs
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.input_val (padsif.input_val [i]),
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// Inouts
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`ifdef VERILATOR // see t_tri_array
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.ana (_anahack [i]),
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`else
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.ana (padsif.ana [i]),
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`endif
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// Inputs
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.pullup_en (padsif.pullup_en [i]),
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.pulldown_en (padsif.pulldown_en [i]),
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.output_en (padsif.output_en [i]),
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.output_val (padsif.output_val [i]),
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.slew_limit_en (padsif.slew_limit_en[i]),
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.input_en (padsif.input_en [i])
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/*AUTOINST*/);
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PADTYPE_VDD:
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begin
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pad_vdd #( .ID( i ) )
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i_pad_vdd(
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.pad (pad[i])
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/*AUTOINST*/);
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// Not SV standard, yet... assign padsif.input_val[i] = ();
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end
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PADTYPE_GND:
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begin
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pad_gnd #( .ID( i ) )
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i_pad_gnd(.pad (pad[i])
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/*AUTOINST*/);
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end
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endcase
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end
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endmodule // pads
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