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43 lines
1.1 KiB
Systemverilog
43 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Large test for SystemVerilog
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012.
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// SPDX-License-Identifier: CC0-1.0
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// Contributed by M W Lund, Atmel Corporation.
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module adrdec
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#( parameter
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NSLAVES = 2 )
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(
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// ***************************************************************************
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// Module Interface (interfaces, outputs, and inputs)
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// ***************************************************************************
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// **** Interfaces ****
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genbus_if.adrdec dbus
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);
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// ***************************************************************************
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// Address Decode
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// ***************************************************************************
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// const logic [15:0] adrmap[1:2] = '{}
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always_comb
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begin
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logic sel [1:NSLAVES];
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sel[1] = (dbus.s_adr[1][7:4] == 4'h0);
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sel[2] = (dbus.s_adr[2][7:4] == 4'h1);
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// sel[3] = (dbus.s_adr[3][7:4] == 4'h2);
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dbus.s_sel = sel;
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// for ( i = 1; i <= dbus.aNumSlaves; i++ )
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// begin
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// dbus.s_sel[i] = (dbus.s_adr[i] == adrmap[i]);
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// end
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end
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endmodule // adrdec
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