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599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
8 lines
306 B
Plaintext
8 lines
306 B
Plaintext
%Error: t/t_fuzz_always_bad.v:10:15: Can't find definition of 'a' in dotted variable: 'c.a'
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10 | always @ c.a c:h;
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| ^
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%Error: t/t_fuzz_always_bad.v:10:19: Can't find definition of task/function: 'h'
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10 | always @ c.a c:h;
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| ^
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%Error: Exiting due to
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