mirror of
https://github.com/verilator/verilator.git
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58 lines
1.2 KiB
C++
58 lines
1.2 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include VM_PREFIX_INCLUDE
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unsigned int main_time = 0;
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double sc_time_stamp() { return main_time; }
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VM_PREFIX* topp = nullptr;
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void clockit(int clk1, int clk0) {
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topp->clks = clk1 << 1 | clk0;
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#ifndef T_CLK_2IN_VEC
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topp->c1 = clk1;
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topp->c0 = clk0;
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#endif
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#ifdef TEST_VERBOSE
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printf("[%u] c1=%d c0=%d\n", main_time, clk1, clk0);
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#endif
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topp->eval();
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main_time++;
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}
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int main(int argc, char* argv[]) {
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Verilated::debug(0);
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Verilated::commandArgs(argc, argv);
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topp = new VM_PREFIX;
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topp->check = 0;
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clockit(0, 0);
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main_time += 10;
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for (int i = 0; i < 2; i++) {
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clockit(0, 0);
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clockit(0, 1);
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clockit(1, 1);
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clockit(0, 0);
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clockit(1, 1);
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clockit(1, 0);
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clockit(0, 0);
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clockit(0, 1);
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clockit(1, 0);
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clockit(0, 0);
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}
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topp->check = 1;
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clockit(0, 0);
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topp->final();
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VL_DO_DANGLING(delete topp, topp);
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}
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