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21 lines
491 B
Systemverilog
21 lines
491 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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rand int unsigned v;
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endclass
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module t_randomize_method_with_bad();
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function automatic int unsigned in_mod_function();
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return 5;
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endfunction
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initial begin
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Foo foo = new;
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int res = foo.randomize() with { v < in_mod_function(); };
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end
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endmodule
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