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19 lines
401 B
Systemverilog
19 lines
401 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class cls;
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task t; t; endtask
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task pre_randomize;
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t;
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endtask
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endclass
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module t;
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cls obj;
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task static t;
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int _ = obj.randomize() with {1 == 1;};
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endtask
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endmodule
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