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30 lines
1.1 KiB
Python
Executable File
30 lines
1.1 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt_all')
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test.compile(verilator_flags2=["--stats"])
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test.file_grep(test.stats, r'Optimizations, Split always\s+(\d+)', 0)
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# Important: if reorder succeeded, we should see no dly vars.
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# Equally important: twin test t_alw_noreorder should see dly vars,
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# is identical to this test except for disabling the reorder step.
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for filename in (test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.h") +
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test.glob_some(test.obj_dir + "/" + test.vm_prefix + "*.cpp")):
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test.file_grep_not(filename, r'dly__t__DOT__v1')
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test.file_grep_not(filename, r'dly__t__DOT__v2')
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test.file_grep_not(filename, r'dly__t__DOT__v3')
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test.execute()
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test.passes()
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