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67ea819d82
Documentation states that minimum of all reported coverage of all signals in a line should be taken. Previous logic would break if there were any signals with zero coverage followed by signals with nonzero coverage - a minimum from those nonzero toggle count would be taken, disregarding zero coverage of previous signals. Internal-tag: [#62193] Signed-off-by: Krzysztof Obłonczek <koblonczek@antmicro.com>
23 lines
587 B
Systemverilog
23 lines
587 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2024 by Antmicro. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t();
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logic[1:0] a;
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logic[1:0] b;
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logic[1:0] c;
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initial begin
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#1 a = 2'b01;
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#1 b = 2'b10;
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#1 c = 2'b11;
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#1 c = 2'b10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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