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27 lines
620 B
Systemverilog
27 lines
620 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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int m_one;
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constraint cons { m_one > 0 && m_one < 2; }
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function int get_constraint_mode;
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return constraint_mode();
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endfunction
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endclass
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module t;
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Packet p;
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initial begin
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p = new;
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p.m_one.constraint_mode(0);
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$display("p.constraint_mode()=%0d", p.constraint_mode());
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$display(p.constraint_mode(0));
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p.cons.constraint_mode();
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end
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endmodule
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