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34 lines
662 B
Systemverilog
34 lines
662 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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endclass
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class Cls extends Base;
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typedef int txn_type_t; // Bad type
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rand txn_type_t req_txn_type;
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static function txn_type_t generate_txn();
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txn_type_t txn = new;
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txn_type_t copy = new txn;
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return txn;
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endfunction
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endclass
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module t(/*AUTOARG*/);
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initial begin
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Base b = Cls::generate_txn();
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$display("%p", b);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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