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23 lines
459 B
Systemverilog
23 lines
459 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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clk
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);
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input clk;
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int cyc = 0;
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logic val = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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val = ~val;
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end
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assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5);
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endmodule
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