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git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
30 lines
610 B
Verilog
30 lines
610 B
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`include "verilated.v"
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module t_clk_flop (/*AUTOARG*/
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// Outputs
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q, q2,
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// Inputs
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clk, clk2, a
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);
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parameter WIDTH=8;
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input clk;
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input clk2;
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input [(WIDTH-1):0] a;
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output [(WIDTH-1):0] q;
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output [(WIDTH-1):0] q2;
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reg [(WIDTH-1):0] q;
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reg [(WIDTH-1):0] q2;
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always @ (posedge clk) q<=a;
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always @ (posedge clk2) q2<=a;
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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