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62 lines
1.7 KiB
Systemverilog
62 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug991
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module t (/*AUTOARG*/);
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typedef struct {
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logic [31:0] arr [3:0];
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} a_t;
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typedef struct {
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logic [31:0] arr [0:3];
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} b_t;
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a_t array_assign;
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a_t array_other;
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b_t larray_assign;
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b_t larray_other;
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initial begin
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array_assign.arr[0] = 32'd1;
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array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2};
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array_other.arr[0] = array_assign.arr[0]+10;
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array_other.arr[3:1] = array_assign.arr[3:1];
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if (array_other.arr[0] != 11) $stop;
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if (array_other.arr[1] != 2) $stop;
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if (array_other.arr[2] != 3) $stop;
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if (array_other.arr[3] != 4) $stop;
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larray_assign.arr[0] = 32'd1;
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larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2};
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larray_other.arr[0] = larray_assign.arr[0]+10;
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larray_other.arr[1:3] = larray_assign.arr[1:3];
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if (larray_other.arr[0] != 11) $stop;
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if (larray_other.arr[1] != 4) $stop;
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if (larray_other.arr[2] != 3) $stop;
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if (larray_other.arr[3] != 2) $stop;
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larray_other.arr = '{5, 6, 7, 8};
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if (larray_other.arr[0] != 5) $stop;
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if (larray_other.arr[1] != 6) $stop;
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if (larray_other.arr[2] != 7) $stop;
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if (larray_other.arr[3] != 8) $stop;
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larray_other.arr = larray_assign.arr;
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if (larray_other.arr[0] != 1) $stop;
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if (larray_other.arr[1] != 4) $stop;
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if (larray_other.arr[2] != 3) $stop;
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if (larray_other.arr[3] != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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