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46 lines
950 B
Verilog
46 lines
950 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk, fastclk, reset_l
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);
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input clk /*verilator sc_clock*/;
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input fastclk /*verilator sc_clock*/;
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input reset_l;
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output passed;
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reg [31:0] count_c;
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reg [31:0] count_f;
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always @ (posedge clk) begin
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if (!reset_l) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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count_c <= 32'h0;
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// End of automatics
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end else begin
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count_c <= count_c + 1;
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end
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end
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always @ (posedge fastclk) begin
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if (!reset_l) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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count_f <= 32'h0;
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passed <= 1'h0;
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// End of automatics
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end else begin
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count_f <= count_f + 1;
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if (count_f == 5) passed <= 1'b1;
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end
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end
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endmodule
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