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29 lines
596 B
Systemverilog
29 lines
596 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [95:0] wide;
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initial begin
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// internal code coverage for _vl_debug_print_w
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wide = {32'haa, 32'hbb, 32'hcc};
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$c("_vl_debug_print_w(",$bits(wide),",",wide,");");
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end
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// Test loop
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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